Description Syntronic China R&D Center is looking for SOC UVM Engineer. Responsibilities > Proficient of System Verilog program capability. > Experience on Python/Perl/Makefile script. > Experience on C/C++ or more SystemC modeling languages. > Experience on UVM project time plan、environment construction、Test case generation and coverage analysis. > Experience on the CHI protocol, CXL and PCIE6-FLIT, and low-power related verification is preferred > Experience on One or more of the AMBA ACE、PCIE、DDR、MAC/PHY Verification related is preferred Requirements > Bachelor’s or master’s degree of communication, Computer Science, Electrical Engineering or related is preferred. >3 Years experience. > Product development knowledge and Product Lifecycle Management knowledge. > Basic English, both spoken and written. > Excellent communication skills.
About Syntronic Syntronic is a prominent engineering Design House specializing in the design and development of electronics, electro-mechanics, embedded and IT software. As the established engineering design house we are, we can provide a valuable contribution to your product and test developments as well as helping you achieve the desired product in time-to-market in a cost-effective way. We also offer solutions where we undertake a turnkey responsibility of product development and system integration from idea to complete system delivery. We have adopting the latest technologies in electronics design and software development worldwide. Among our customers and partners are some of the world’s most technique-intensive businesses and organizations in sectors such as telecommunication, automotive, defence and medicine industries. We design to satisfy customers' needs, we are focusing on quality, competence and ease of production. For more information about Syntronic, please see www.syntronic.com We are looking for competent, hard working engineers with good design experience especially within the electronic area. Welcome to join us!